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DATASHEET
28-BIT 1:2 REGISTERED BUFFER WITH PARITY
IDT74SSTUBF32865A
The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
Description
This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The IDT74SSTUBF32865A operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high, and CLK going low. The device supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs except PTYERR are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the IDT74SSTUBF32865A must ensure that the outputs will remain low, thus ensuring no glitches on the output. The device monitors both DCS0 and DCS1 inputs and will gate the Qn outputs from changing states when both DCS0 and DCS1 are high. If either DCS0 and DCS1 input is low, the Qn outputs will function normally. The RESET input has priority over the DCS0 and DCS1 control and will force the Qn outputs low and the PTYERR output high. If the DCS-control functionality is not desired, then the CSGateEnable input can be hardwired to ground, in which case, the setup-time requirement for DCS would be the same as for the other D data inputs.
Features
* 28-bit 1:2 registered buffer with parity check functionality * Supports SSTL_18 JEDEC specification on data inputs * * *
and outputs Supports LVCMOS switching levels on CSGateEN and RESET inputs Low voltage operation: VDD = 1.7V to 1.9V Available in 160-ball LFBGA package
Applications
* DDR2 Memory Modules * Provides complete DDR DIMM solution with
ICS98ULPA877A or IDTCSPUA877A
* Ideal for DDR2 400, 533, 667, and 800
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Block Diagram
(CS ACTIVE) VREF
PARIN
D R
Q
22
PARITY GENERATOR AND CHECKER
PTYERR
Q0A D0 D R Q Q0B
Q21A D21 D R Q Q21B
QCS0A DCS0 D R CSGateEN QCS1A DCS1 D R Q QCS1B Q QCS0B
DCKE0, DCKE1
QCKE0A, QCKE1A
2
D R
Q
2
QCKE0B, QCKE1B QODT0A, QODT1A
DODT0, DODT1
2
D R
Q
2
QODT0B, QODT1B
RESET CLK CLK
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Pin Configuration
1 A
2
3
4
5
6
7
8
9
10
11 12
1 A
VREF D1 D3 D6 D7 D11 D18 CSGate EN CLK CLK RESET D0 D17 D19 D13 DODT1 DCKE0 VREF
2
NC D2 D4 D5 D8 D9 D12 D15 DCS0 DCS1 D14 D10 D16 D21 D20 DODT0 DCKE1 MCL
3
PARIN NC
4
NC NC
5
NC NC
6
QCKE1A
7
QCKE0A
8
Q21A Q21B
9
Q19A Q19B
10
Q18A Q18B
11
Q17B QODT0B QODT1B
12
Q17A QODT0A QODT1A Q20A Q16A Q1A Q2A Q5A QCS0A QCS1A Q6A Q10A Q9A Q11A Q15A Q14A Q8B Q8A
B C D E F G H J K L M N P R T U V
B C D E F G H J K L M N P R T U V
QCKE1B
QCKE0B
VDDL VDDL VDDL VDDL VDDL GND VDDL GND GND VDDL GND GND
GND GND GND GND GND GND VDDL GND GND VDDL VDDL VDDL
NC VDDL
NC VDDR
GND GND VDDR VDDR GND VDDR GND VDDR GND VDDR
GND GND VDDR VDDR GND VDDR GND VDDR GND VDDR GND GND
Q20B Q16B Q1B Q2B Q5B QCS0B QCS1B Q6B Q10B Q9B Q11B Q15B Q14B
VDDL VDDL
VDDR GND
VDDR GND
MCL MCL
PTYERR NC
MCH MCH
Q3B Q3A
Q12B Q12A
Q7B Q7A
Q4B Q4A
Q13B Q13A
Q0B Q0A
160-Ball BGA TOP VIEW
NOTE: 1. An empty cell indicates no ball is populated at that gridpoint. NC denotes a no-connect (ball present but not connected to the die). MCL denotes a pin that Must be Connected LOW. MCH denotes a pin that Must be Connected HIGH.
160-Ball BGA TOP VIEW
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Ball Assignment
Signal Group
Ungated Inputs Chip Select Gated Inputs
Signal Name
DCKE0, DCKE1, DODT0, DODT1 D0 ... D21
Type
SSTL_18 SSTL_18
Description
DRAM function pins not associated with Chip Select. DRAM inputs, re-driven only when Chip Select is LOW. DRAM Chip Select signals. These pins initiate DRAM address/command decodes, and as such at least one will be low when a valid address/command is present. The register can be programmed to re-drive all D-inputs only (CSGateEN high) when at least one Chip Select input is LOW. Outputs of the register, valid after the specified clock count outputs and immediately following a rising edge of the clock. Input parity is received on pin PARIN and should maintain odd parity across the D0...D21 inputs, at the rising edge of the clock. When LOW, this output indicates that a parity error was output identified associated with the address and/or command inputs. PTYERR will be active for two clock cycles, and delayed by an additional clock cycle for compatibility with final parity out timing on the industry-standard DDR-II register with parity (in JEDEC definition).
Chip Select Inputs
DCS0, DCS1
SSTL_18
Re-Driven
Q0A...Q21A, Q0B...Q21B, QCSnA,B QCKEnA,B, QODTnA,B PARIN
SSTL_18
Parity Input
SSTL_18
Parity Error
PTYERR
Open Drain
Program Inputs
CSGateEN
Chip Select Gate Enable. When HIGH, the D0..D21 inputs will be latched only when at least one Chip 1.8V LVCMOS Select input is LOW during the rising edge of the clock. When LOW, the D0...D21 inputs will be latched and redriven on every rising edge of the clock. SSTL_18 Differential master clock input pair to the register. The register operation is triggered by a rising edge on the positive clock input (CLK). Must be connected to a logic LOW or HIGH. SSTL_18 Asynchronous reset input. When LOW, it causes a reset of the internal latches, thereby forcing the outputs LOW. RESET also resets the PTYERR signal. Input reference voltage for the SSTL_18 inputs. Two pins (internally tied together) are used for increased reliability.
Clock Inputs
CLK, CLK MCL, MCH RESET
Miscellaneous Inputs
VREF
0.9V nominal
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Function Table
Inputs1 RESET DCS0 DCS1 CSGate EN
X X X X X X X X X L L L H H H X or Floating
Outputs CLK CLK Dn, DODTn, DCKEn
L H X L H X L H X L H X L H X X or Floating
Qn
QCS0x QCS1x QODT, QCKE
L L Q0 L L Q0 H H Q0 H H Q0 H H Q0 L L L Q0 H H Q0 L L Q0 H H Q0 H H Q0 L L H Q0 L H Q0 L H Q0 L H Q0 L H Q0 L
H H H H H H H H H H H H H H H L 1
L L L L L L H H H H H H H H H X or Floating
L L L H H H L L L H H H H H H X or Floating
L or H L or H L or H L or H L or H
L or H L or H L or H L or H L or H
L H Q0 L H Q0 L H Q0 L H Q0 Q0 Q0 Q0 L
X or X or Floating Floating
H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW to HIGH = HIGH to LOW
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Parity and Standby Function Table
Inputs1 RESET
H H H H H H H H H H L 1
Outputs of Inputs = H (D1 - D21)
Even Odd Even Odd Even Odd Even Odd X X X or Floating
DCS0
L L L L X X X X H X X or Floating
DCS1
X X X X L L L L H X X or Floating
CLK
L or H X or Floating
CLK
L or H X or Floating
PARIN2
L L H H L L H H X X X or Floating
PTYERR3
H L L H H L L H PTYERR0 PTYERR0 H
H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW to HIGH = HIGH to LOW 2 PARIN arrives one clock cycle after the data to which it applies. 3 This transition assumes PTYERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If PTYERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW.
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Absolute Maximum Ratings
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Supply Voltage, VDD Input Voltage Range, VI Output Voltage Range,
1
Rating
-0.5V to 2.5V -0.5V to VDD + 2.5V -0.5V to VDDQ + 0.5V 50mA 50mA 50mA 100mA 44.3C/W 38.1C/W -65 to +150C 0m/s Airflow 1m/s Airflow
VO1,2
Input Clamp Current, IIK Output Clamp Current, IOK Continuous Output Clamp Current, IO Continuous Current through each VDD or GND Package Thermal Impedance (ja)3 Storage Temperature
1 The input and output negative voltage ratings may be exceeded if the ratings of the I/P and O/P clamp current are observed. 2 This current will flow only when the output is in the high state level VO > VDDQ. 3 The package thermal impedance is calculated in accordance with JESD 51.
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Operating Characteristics
The RESET and CSGateEN inputs of the device must be held at valid levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is LOW. Symbol VDD VREF VTT VI VIH VIL VIH VIL VIH VIL VICR VID IOH IOL IERROL TA
Parameter
I/O Supply Voltage Reference Voltage Termination Voltage Input Voltage AC High-Level Input Voltage Dn, PARIN, AC Low-Level Input Voltage DCSn, DCKEn, DC High-Level Input Voltage DODTn DC Low-Level Input Voltage High-Level Input Voltage Low-Level Input Voltage Common Mode Input Range Differential Input Voltage High-Level Output Current Low-Level Output Current PTYERR LOW Level Output Current Operating Free-Air Temperature RESET, CSGateEN CLK, CLK
Min.
1.7 0.49 * VDD VREF - 0.04 0 VREF + 0.25
Typ.
1.8 0.5 * VDD VREF
Max.
1.9 0.51 * VDD VREF + 0.04 VDD VREF - 0.25
Units
V V V V
VREF + 0.125 VREF - 0.125 0.65 * VDDQ 0.35 * VDDQ 0.675 600 -8 8 25 0 +70 1.125
V
V V mV mA mA C
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DC Electrical Characteristics Over Operating Range
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, VDD = 1.8V 0.1V. Symbol Parameter VOH VOL VERROL IIL Output HIGH Voltage Output LOW Voltage PTYERR Output LOW Voltage All Inputs Static Standby
Test Conditions
IOH = -6mA, VDDQ = 1.7V IOL = 6mA, VDDQ = 1.7V IERROL = 25mA, VDD = 1.7V VI = VDD or GND; VDD = 1.9V IO = 0, VDD = 1.9V, RESET = GND IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK = CLK = VIH(AC) or VIL(AC) IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK = VIH(AC), CLK = VIL(AC) IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle. VI = VREF 350mV VICR = 1.25V, VIPP = 360mV VI = VDD or GND
Min.
1.2
Typ.
Max.
0.5 0.5
Units
V V V A A
-5 200
+5
10 mA 120 A/Clock MHz A/Clock MHz/ Data 3 3.5 5 pF
IDD
Static Operating
Dynamic Operating (clock only) IDDD Dynamic Operating (per each data input) Dn, PARIN CIN CLK and CLK RESET
300
40
2 2.5
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Timing Requirements Over Recommended Operating Free-Air Temperature Range
VDD = 1.8V 0.1V Symbol
fCLOCK tW tACT tINACT
Parameter
Clock Frequency Pulse Duration; CLK, CLK HIGH or LOW Differential Inputs Active Time
1 2
Min.
1
Max.
410 10 15
Units
MHz ns ns ns
Differential Inputs Inactive Time
tSU
Setup Time
DCS0 before CLK, CLK, DCS and CSGateEN HIGH; DCS1 before CLK, CLK, DCS0 and CSGateEN HIGH3 DCSn, DODT, DCKE, and Dn after CLK, CLK PARIN after CLK, CLK DCSn, DODT, DCKE, and Dn after CLK, CLK PARIN after CLK, CLK
0.6 ns 0.5 0.5 0.4 0.4 ns
tH
Hold Time
1 VREF must be held at a valid input voltage level and data inputs must be held at valid logic levels for a minimum time of tACT(max) after RESET is taken HIGH. 2 VREF, data, and clock inputs must be held at a valid input voltage levels (not floating) for a minimum time of tINACT(max) after RESET is taken LOW. 3 tSU = 700ps for DCSx exiting Suspention Mode.
Switching Characteristics Over Recommended Free Air Operating Range (unless otherwise noted)
VDD = 1.8V 0.1V Symbol
fMAX tPDM
1
Parameter
Max Input Clock Frequency Propagation Delay, single bit switching, CLK to CLK to Qn Propagation Delay, single-bit switching, CLK / CLK to Qn
Min.
410 1.1 0.4 1.2 1
Max.
1.5 0.8 1.6 3 3 3 3
Units
MHz ns ns ns ns ns ns ns
tPDQ2 tPDMSS tLH tHL tPHL tPLH 1 2
1
Propagation Delay, simultaneous switching, CLK to CLK to Qn LOW to HIGH Propagation Delay, CLK to CLK to PTYERR HIGH to LOW Propagation Delay, CLK to CLK to PTYERR HIGH to LOW Propagation Delay, RESET to Qn LOW to HIGH Propagation Delay, RESET to PTYERR
Design target as per JEDEC specifications. Production Test. (See Production Test Circuit in TEST CIRCUIT AND WAVEFORM section.)
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Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range
VDD = 1.8V 0.1V Parameter
dV/dt_r dV/dt_f dV/dt_ 1
1
Min.
1 1
Max.
4 4 1
Units
V/ns V/ns V/ns
Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).
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Parity Logic Diagram
Dn
22 22
D
Q
QnA
QnB
D
D
LATCHING AND RESET FUNCTION
PTYERR
PARIN
D
CLOCK
Register Timing
n-1 CLK CLK tSU Dn tSU PARIN tPDM, tPDMSS Qn tH tH n n +1 n+2 n+3 n+4 n+5
tPDM PTYERR
tPDH
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Test Circuits and Waveforms (VDD = 1.8V 0.1V)
VDD
VDD/2
RL = 1K
DUT
TL = 50 CLK Inputs CLK CLK Test Point RL = 100 Test Point Out CL = 12 pF TL = 350ps, 50
ZO = 50
Test Point Test Point
DUT
CLK Test Point Out CLK RL = 50 ZO = 50
Test Point RL = 1K
CLK Inputs ZO = 50
Production-Test Load Circuit Simulation Load Circuit
CLK CLK VICR tPLH Output VTT VICR tPHL VOH VTT VOL VID
LVCMOS RESET Input tINACT IDD
VDD VDD/2 VDD/2 0V tACT 90% 10%
LVCMOS RESET Input
Voltage Waveforms - Propagation Delay Times
VIH VDD/2 VIL tRPHL VOH
Voltage and Current Waveforms Inputs Active and Inactive Times
Output
VTT VOL
tW Input VICR VICR VID
Voltage Waveforms - Propagation Delay Times NOTES: 1. CL includes probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA 3. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, Zo = 50, input slew rate = 1 V/ns 20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VTT = VREF = VDD/2 6. VIH = VREF + 250mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 250mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600mV. 9. tPLH and tPHL are the same as tPDM.
Voltage Waveforms - Pulse Duration
CLK VICR CLK tSU Input VREF tH VIH VREF VIL VID
Voltage Waveforms - Setup and Hold Times
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Test Circuits and Waveforms (VDD = 1.8V 0.1V)
VDD VDD
DUT
Out
RL = 50 Test Point
DUT
Out
RL = 1K Test Point
CL = 10 pF
CL = 10 pF
Load Circuit: High-to-Low Slew-Rate Adjustment
Load Circuit: Error Output Measurements
Output 80%
VOH
LVCMOS RESET Input tPLH
VCC VCC/2 0V
20% dv_f dt_f VOL
VOH Output Waveform 2 0.15V 0V
Voltage Waveforms: High-to-Low Slew-Rate Adjustment
Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with respect to RESET input)
DUT
Out CL = 10 pF Test Point RL = 50
Timing Inputs
VICR tHL
VICR
VI(PP)
Output Waveform 1
VCC VCC/2 VOL
Load Circuit: Low-to-High Slew-Rate Adjustment
Voltage Waveforms: Open Drain Output High-to-Low Transition Time (with respect to clock inputs)
dt_r dv_r 80% VOH
Timing Inputs
VICR tHL
VICR
VI(PP)
VOH
20% Output VOL
Output Waveform 2
0.15V
0V
Voltage Waveforms: Low-to-High Slew-Rate Adjustment
Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with respect to clock inputs)
NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, Zo = 50, input slew rate = 1 V/ns 20% (unless otherwise specified).
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Package Outline and Package Dimensions - BGA
Package dimensions are kept current with JEDEC Publication No. 95
0.925 Ref ROW A, COLUMN 1 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H D J K d L M N P R T U V E T h e TYP
b C
0.975 Ref
0.10
C
ALL DIMENSIONS IN MILLIMETERS D 13.00 Bsc E 9.00 Bsc T Min/Max 1.10/1.30 BALL GRID e 0.65 Bsc Horiz 12 Vert 18 Total 160 d Min/Max 0.35/0.45 h Min/Max 0.27/0.37 REF. DIMS b 0.975 c 0.925
NOTE: Ball grid total indicates maximum ball count for package. Lesser quantity may be used.
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Ordering Information
IDT XX SSTUBF XX Family Temp. Range XXX XX Device Type Package X Shipping Carrier 8 Tape and Reel
BKG
Thin Profile, Fine Pitch, Ball Grid Array - Green
865A
28-Bit 1:2 Registered Buffer with Parity
32 74
Double Density 0C to +70C (Commercial)
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www.IDT.com
For Sales
800-345-7015 408-284-8200 Fax: 408-284-2775
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505
Europe
IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339
(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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